Electronic circuits, such as integrated circuits, are used in a variety of electronic systems, from automobiles to microwaves to personal computers. Designing and fabricating integrated circuits typically involves many steps, known as a “design flow.” The particular steps of a design flow often are dependent upon the type of integrated circuit being designed, its complexity, the design team and the integrated circuit fabricator or foundry that will manufacture the circuit. Software and hardware “tools” are typically used at various stages of the design flow to aid in developing the design and in ensuring that the design is free from errors. The process of using hardware and software tools to aid in the design flow is often referred to as electronic design automation (EDA).
Several steps are common to most design flows. Typically, the specification for a new circuit is first described at a very abstract level. More particularly, relationships between a set of inputs and a set of outputs are described using a set of computations. This is referred to as an “algorithmic level” design or “algorithmic specification” and is often described using conventional computer programming languages, such as, for example, C++. The algorithmic specification is then subsequently transformed, often referred to as “synthesized,” into a design having a lower level of abstraction. Typically, designers synthesize the algorithmic specification into a Register Transfer Level (RTL) description of the circuit. With this type of description, the circuit is defined in terms of both the exchange of signal between hardware registers and the logical operations that are performed on those signals.
During various stages of the design flow, the behavior of the design is checked to ensure that it corresponds with the intended or expected behavior. This is often referred to as “verification.” As those of ordinary skill in the art will appreciate, verification can be facilitated by a number of different methods. For example, formal verification methods utilize mathematical proofs to ensure that a designs behavior matches the intended behavior. Alternatively, a design could be simulated to aid in verification. More specifically, a software application can interpret a design, such as, for example, an algorithmic specification or a register transfer level design, and then provide a simulated set of outputs for a given set of inputs. These simulated outputs can then be used to verify the integrity of the design and make corrections where needed. As the electronic design is synthesized to lower and lower levels of abstraction, the verification process is often repeated.
As verification is often used on electronic designs having an abstract level of representation, such as, for example, an algorithmic design or a register transfer level design it can be difficult to correlate errors in the verification process to specific portions of a design. Accordingly, designers will often use a visualization tool to assist in debugging a design based upon the results of verification. More specifically, a visualization of the design, such as, for example, a finite state machine representation of the design, is often used to assist designers in tracking down erroneous states and transitions. By using a finite state machine visualization of a design, designers can graphically visualize the various states and transitions within a design. Subsequently, this visualization can be used in conjunction with the results of verification to more efficiently track down errors in the design, such as, for example, power management errors.
Conventional visualization tools typically extract the various states and transitions from the abstract representation of the design. For example, a state machine representation of a design can be extracted from a register transfer level description. As those of ordinary skill in the art will appreciate, modern electronic designs have increasingly complex power needs. As such, a second description, specific to the power behavior of the design is typically added at the register transfer level. Accordingly, many electronic designs are described using a power specification and a logical specification. Thus, a visualization that only describes the logical behavior of the circuit is often insufficient to describe the entire design behavior of modern designs.
As the complexity of the power behavior of electronic designs increases, such as, for example, with added power domains and modes, verification and visualization tools that can account for this increase in complexity are needed. Although conventional visualization tools are capable of generating simple finite state machine representations of the design behavior of a design, they are incapable of generating complex representations, such as, for example, a hierarchical representation of the power behavior of a design.